1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a DRAM type semiconductor memory device capable of storing information of a plurality of bits in one memory cell.
2. Description of the Related Art
As a technique for highly integrating a dynamic type semiconductor memory device, Japanese Patent Application Laid-open No. 3-16094 is known. In this prior art, information in an amount of two bits is stored using three elements comprising two transistors and one capacitor, and a memory element structure of 1.5 element per one bit is disclosed.
FIG. 1 shows the conventional semiconductor memory device disclosed in the above publication, and shows memory cells and circuits for reading and writing. FIG. 2 is for showing input waveforms for explaining the operation of FIG. 1. FIGS. 3 and 4 are for showing waveforms when a bit line is read to show the operation of the circuit in FIG. 1.
As shown in FIG. 1, in the memory cell array, a memory cell 20 is a memory cell which accumulates information in an amount of two bits in the two transistors and the one capacitor. Transfer gates 22 and 23 are for reading information in an accumulation capacitor 21, the reference numbers 24 and 25 represent accumulation nodes. The reference numbers 26 and 27 represent sense amplifiers.
Next, with reference to input timing waveforms shown in FIG. 2, the operation of the circuit of the above-described semiconductor memory device will be explained. At a time t0, if bit line equalize control signals NEQ and PEQ are varied as shown in FIG. 2, all transistors in a bit line equalize circuit are turned OFF, a precharge of the bit line is completed, and all voltages becomes 1/2 Vcc.
Subsequently, as the memory cell 20 is connected to bit line pair BLL1 and BLL1 (BLL1 is a complementary signal of BLL1), a CUT2 low signal turns off a transistor, which is connected to CUT 2, that is part of a circuit for cutting off the bit line from the sense amplifier, and raises a word line WLL1 at a time t1.
With this operation, information accumulated in the accumulation capacitor 21 is charge transferred to bit lines BLL1, BLR1, SBL1, SBL2 and BLL1, BLR1, SBL1, SBL2.
Further, at a time t2, if CUT1 and REQ are low, the bit line on the side of the memory cell is cut off from the sense amplifier, and SBL1 and SBL2 are also cut off from SBL1 and SBL2, respectively. With this, both the sense amplifiers 26 and 27 are independently provided with the same information as in the memory cell 20.
Then, after UP and DOWN are varied as shown in FIG. 2 at a time t3, sense amplifier action is started by SAS at a time t4, and CUT1 and CUT2 are raised at a time t5 to connect the sense amplifier to a bit line at a side of the memory cell to carry out a pull up by SAS.
Finally, CSEL is pulled down at a time t7, the amplified information of the memory cell is transferred to a data line to complete the reading operation.
Since this conventional memory cell accumulates information of two bit in one accumulation capacitor, when the memory cell holds information, there are four kinds of states of voltages of the accumulation nodes 24 and 25 as shown in Table 1 below. Data in the Table shows information which is output to data lines D1 and D2, and H and L correspond to Vcc and GND voltages, respectively.
TABLE 1 ______________________________________ D1 = H D1 = H D1 = L D1 = L Data D2 = H D2 = L D2 = H D2 = L ______________________________________ Node 24 Vcc 2/3 Vcc 1/3 Vcc GND Node 25 GND 1/3 Vcc 2/3 Vcc Vcc ______________________________________
Among them, FIG. 3 shows the state when information of D1=H and D2=H are read out, and FIG. 4 shows the state when information of D1=H and D2=L are read out.
When information of D1=H and D2=H are read out, as shown in FIG. 3, a potential difference of .DELTA.V is generated between the complementary bit lines at the time t1 when the word line is raised as shown in FIG. 3. At the time t3, electric potentials of the SBL1 and SBL2 are raised by 1/3.DELTA.V by means of UP and DOWN signals, and electric potentials of SBL1 and SBL2 are lowered by 1/3.DELTA.V on the other hand.
However, voltages of the SBL1 and SBL1, as well as SBL2 and SBL2 are not reversed, and after the sense operation from time t4 onward, Vcc level is output to both the D1 and D2.
On the other hand, when information of D1=H and D2=L are read out, as shown in FIG. 4, at the time t1 when the word line is raised, potential difference of only 1/3.DELTA.V is generated in between the complementary bit lines. Thereupon, at time t3, if potentials of the SBL1 and SBL2 are raised by 1/3.DELTA.V by UP and DOWN signals, and potentials of the SBL1 and SBL2 are lowered by 1/3.DELTA.V on the other hand, the potentials of the SBL2 and SBL2 are reversed. Therefore, after the sense operation from time t4 onward, Vcc is output to D1, and GND level is output to D2.
However, the above described conventional semiconductor memory device is different in a structure of memory array from the both electrodes of the capacitor to a conventional general dynamic RAM having a memory cell comprising one transistor and one capacitor and therefore, their producing methods are also different.
Further, since it is necessary to pull out wires from the complementary bit lines through two transistors, if it is to be highly integrated, it is difficult to layout while maintaining symmetry, and this fact brings out deterioration of margin (reading out margin).
Thereupon, for the purpose of highly integrating a dynamic type semiconductor memory device, the present applicant has already proposed a dynamic type semiconductor memory device capable of accumulating information in an amount two bits in one memory cell even if a conventional memory array comprising one transistor and one capacitor is used (Japanese Patent Application Laid-Open No. 8-352635). Although this senior application has not been opened, there is described a dynamic type semiconductor memory device capable of storing information in an amount of two bits in one memory cell as in the present invention, and this senior application relates to the present invention, the dynamic type semiconductor memory device of the senior application will be first explained.
The semiconductor memory device described in the above-described Japanese Patent Application Laid-Open No. 8-352635 will be explained below with reference to FIGS. 5 to 9. FIG. 5 is a block diagram of a memory cell array and an auxiliary sense amplifier SSA. FIG. 6 is a circuit diagram showing one example of a conventional auxiliary sense amplifier SSA shown in FIG. 5. FIG. 7 shows input timing waveforms for explaining operation of the conventional auxiliary sense amplifier SSA shown in FIG. 6, and FIG. 8 shows bit line operation waveforms at the time of reading out operation for explaining operations of FIGS. 5 and 6.
In FIG. 5, the bit lines are hierarchically layered into a complementary main bit line pair GBLTj, GBLNj and auxiliary bit line pair BLTij and BLNij. One set of main bit lines are connected to one main sense amplifier and a plurality of auxiliary sense amplifiers SSA, which connections are not shown.
With reference to the input timing waveforms shown in FIG. 7, the operation of circuit of the semiconductor memory device shown in FIGS. 5 and 6 will be explained.
As shown in FIG. 7, if PDL which is a precharge control signal of the auxiliary bit line is varied from H level to L level at time t0, all the transistors of the auxiliary bit line precharge circuit shown in FIG. 6 are turned OFF, the precharge in FIG. 6 is completed. Voltages of the auxiliary bit lines SBLTj, SBLNj, BLTij and BLNij remain 1/2 Vcc. Further, at time t0, transfer gates SG1, SG2 and SG3 vary from H level to L level, and SG0 remains H level. That is, among four auxiliary bit line pair commonly used by one auxiliary sense amplifier, only the auxiliary bit line pair selected at SG0 are first connected to the auxiliary sense amplifier, and reading out and re-writing are carried out.
Next, at time t1, if the word line WL is varied from L level to H level, an information accumulated in the memory cell connected to the word line WL is read out by the auxiliary bit line BLTij all together.
Since the semiconductor memory device shown in FIGS. 5 and 6 accumulates information of two bits in one memory, when the memory cell holds the information, there are four kinds of voltages of the accumulation nodes, i.e., power source voltages Vcc, 2/3 Vcc, 1/3 Vcc and GND (ground potential). These four states respectively correspond to "11", "10", "01" and "00" which are binary numbers of two bits.
At time t1, after the word line is raised, if a potential difference generated between the complementary auxiliary bit line pair when the memory cell holds information "11"is defined as .DELTA.V, a potential difference of 1/3.DELTA.V is generated between the complementary auxiliary bit line pair when the memory cell holds information "10".
FIG. 8 shows an example when memory cells MC02 and MC03 hold information "11" and memory cells MC12 and MC31 hold information "10".
Next, at time t2, if the lead switch signal RS is varied from L level to H level as shown in FIG. 7, readout transistors 3 and 4 of the auxiliary sense amplifier are turned ON, a potential of the main bit line precharged to 1/2 Vcc by a main bit line precharge circuit which is not shown is lowered in accordance with gate voltages of sense transistors 1 and 2, i.e., in accordance with levels of the auxiliary bit line pair. With this, the potential difference which is read out to the auxiliary bit line is transmitted to the main bit lines GBLT and GBLN.
Next, at time t3, the lead switch signal RS is lowered to L level, the potential difference between the GBLT and GBLN is amplified to Vcc level or GND level by the main sense amplifier as shown in FIG. 8. This represents reading out operation of upper bits, and shows that "H" data is read out to the main bit line pair GBLT3 and GBLN3.
While the main bit line pair are amplified (from time t3 to time t4), since signal CPE for controlling the conduction of transfer gates which are respectively connected in series to the capacitors 5 and 6 between the main bit line and the auxiliary bit line is H level, the potentials of the auxiliary bit line pair receive an influence of variation in potential of the main bit line by the capacitors 5 and 6 of the reading out circuit, and the potentials of the auxiliary bit line pair are also varied.
When the memory cell holds information "11", potentials of the auxiliary bit line BLT02 and BLT03 shown in FIG. 8 are lowered by 1/3.DELTA.V, and potentials of BLN02 and BLN03 are raised by 1/3.DELTA.V.
Next, at time t4, TGU and CPE are lowered to L level, and the bit line in the memory array and the sense amplifier are cut off and after that, the potential of the auxiliary bit line is not influenced by the variation in potential of the main bit line.
Then, at time 5, a light switch signal WSU is raised, and the amplified potential of the main bit line is written in the auxiliary bit lines BLTij and BLNij.
Thereafter, at time 6, the light switch signal WSU is lowered, and the potential of the main bit line is precharged to 1/2.DELTA.Vcc.
Next, at time t7, the lead switch signal RS is again activated, and the potential difference between the auxiliary bit lines SBLTj and SBLNj is transmitted to the main bit lines GBLTj and GBLNj and is amplified. At that time, if the memory cell holds information "11", "H" data is again read out, but if the memory cell holds information "10", since the potentials of the SBLTj and SBLNj are reversed as compared with the potentials when upper bits are read out, "L" data is read out. The reading out operation at that time is the reading out operation of lower bits.
Thereafter, at time t9, WSL and TGL are raised as shown in FIG. 7, data in the main bit lines is respectively written in auxiliary bit line pair (not shown) which exist opposite side from the word line WL of the auxiliary sense amplifier SSA. At that time, the auxiliary bit line (not shown) to which lower bit data is written is provided at central portions with multilevel writing transfer gates CTG like the auxiliary bit lines shown in FIG. 5. The transfer gates CTG are turned OFF at that time. Therefore, if the total capacity of the auxiliary bit lines sandwiching the multilevel writing transfer gates CTG is 2 Cb, the upper bit data is written in the auxiliary bit lines having 2 Cb capacity, and the lower bit data is written in the auxiliary bit lines having Cb capacity.
After the light switch signal WSL is raised, if TGU is raised at time t10, four levels are generated on the auxiliary bit line in accordance with data of upper bit and lower bit.
Then, at time t11, SG0 is lowered as shown in FIG. 7, PDL is raised, the auxiliary bit lines SBLTj and SBLNj in the auxiliary sense amplifier are precharged to 1/2 Vcc and then, SG1 is raised at time t12. Therefore, reading out and re-writing operations of the auxiliary bit line pair selected by SG1 are carried out likewise this time. Then, reading out and re-writing operations of the auxiliary bit line pair selected by SG2 and SG3 are sequentially carried out, and finally, the word line WL is raised to complete the series of reading out operation is completed.
However, in the semiconductor memory device described in the above-described senior application, a capacitance Cbb between adjacent bits exists between the adjacent auxiliary bit lines as shown in FIG. 5. Further, in this conventional semiconductor memory device, at the time of reading out and re-writing operations of the auxiliary bit line pair selected by the transfer gate SG0, the auxiliary bit line pair selected by the adjacent SG1 and SG3 are left reading out data from the memory cell and standing by in a floating state. That is, if the memory cells MC03 and MC13 shown in FIG. 5 store "11" and "10" data, respectively, the word line WL is raised and the transfer gate SG0 is selected, and when data is again written to the auxiliary bit lines BLT03 and BLN03 at time t5 shown in FIG. 8, the auxiliary bit line BLT12 adjacent the auxiliary bit line BLN03 receives a noise from capacitance between adjacent bit lines, and reading out potential difference is reduced as shown in FIG. 8. Further, the bit line BLN31 likewise receives a noise from capacitance between adjacent bit lines from the bit line BLT02, and the reading out potential difference is reduced.
For the reason described above, if a fine working technique is progressed, and a rate of capacitance between adjacent bit lines with respect to bit line parasitic capacitance is increased, there is an undesirable possibility that the reading out margin is deteriorated.